A charge detection transistor shown in FIG. 1 is used as an ISFET (ion sensitive field effect transistor) to detect an ion charge in a solution. This transistor is basically similar to a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) except that it does not have a gate electrode, and a gate insulating film is in direct contact with a solution. A more detailed description of the ISFET may be found, for example, in Non-Patent Document 1 in a list shown below.
A source region 2 and a drain region 3 of a high-density N-type diffusion layer are formed in a P-type silicon substrate 1, and a gate insulating film 4 is formed on a surface of the substrate. The gate insulating film 4 is in-contact with a solution 5 in which a reference electrode 6 is disposed. A bias is set such that an inversion layer 7 is formed on a Si surface between the source 2 and the drain 3 thereby to detect an ion charge in the solution from a current flowing through the inversion layer. Normally, the ISFET is operated with a constant current. In this case, a potential difference between the reference electrode 6 and the source 2 is detected. To detect the presence of a particular ion, the potential difference is measured between a solution in which there is no ion and a solution including the ion. However, the potential difference caused by the ion charge is as small as a few tens of millivolts, and thus a special concern is needed in detection thereof.
An example of a conventional ISFET control circuit is shown in FIG. 2. The threshold value of the ISFET varies due to variations in production conditions. However, required resolution is smaller than the variation width in threshold value of as-produced ISFETs. Therefore, to achieve required resolution, gate potential differences are sequentially stored, and measured values are compared before and after measurement. In this method, it is more important to minimize the variation in transistor characteristics and minimize degradation of gate insulation films after production than to minimize the variations that occur during production.
In FIG. 2, the reference electrode is always grounded. A current from a direct-current power source Uref flows through a path including a direct-current connection path passing through a resistor R0, a node N1, and R02 and a direct-current connection path passing though a resistor R03, a node N2, and the ISFET. Potentials of the nodes N1 and N2 are adjusted by an operational amplifier such that the node N1 and the node N2 are at the same potential. As a result, a constant drain current R01Uref/R03(R01+R02) flows through the ISFET, the voltage between the drain and source is maintained at a constant value R02 Uref/(R01+R02), and Uout is determined such that the above-described operating point of the transistor is achieved. The ISFET is used as a source follower thereby to achieve a great detection range. The ISFET is always kept in an ON state so that even if an abnormal charge appears in a solution, such an abnormal charge is compensated for by movement of carries in an inversion layer thereby preventing the gate insulating film from being easily degraded. Furthermore, the drain-to-source voltage is always kept at a relatively low value (for example, 0.5 volts). This prevents hot electrons from being generated and thus prevents the gate insulating film from being degraded and preventing surface states from being created. Diodes D1 and D2 are connected in parallel to Uout whereby the source voltage of the ISFET is always kept at a voltage in the range of −1.3 V to 3 V thereby protecting the ISFET.
Patent Document 1 in a list shown below discloses a technique in which a differential amplifier is formed with a charge detection transistor and a reference transistor such that a difference signal indicating a difference between a state in which there is a substance on a gate and a state in which there is no substance is output thereby achieving an improvement in detection accuracy.
Patent Document 2 in the list shown below discloses a circuit in which a charge detection transistor and a reference transistor are inserted in a path on the drain side of a current mirror circuit so that drain outputs thereof are differentially amplified. Also in this technique, as is in the technique disclosed in Patent Document 1, a difference signal indicating a difference between a state in which there is a substance on a gate and a state in which there is no substance is output thereby achieving an improvement in detection accuracy.
Patent Document 3 discloses a circuit in which a sample measurement electrode connected to a gate electrode of a charge detection transistor is charged, and a substance on the measurement electrode is detected by capacitive voltage division. Patent Document 3 also discloses a technique in which after the gate electrode of the charge detection transistor is charged, the gate is cut off, an attenuation characteristic of a reduction in the gate voltage is measured, and a substance is detected based on an attenuation constant thereof.
Patent Document 5 discloses a technique in which a pressure is measured by detecting a change in a drain voltage that occurs when the pressure is applied while maintaining a gate voltage and a drain current at constant values.
Patent Document 6 discloses a sensor configured to detect a chemical substance on a detection FET by a differential output between the detection FET and a non-detection FET.
Patent Document 7 discloses an apparatus configured to determine the quantity of nucleic acid using elements having various detection areas. In any technique disclosed in Documents cited above, differential amplification is used.    Non-Patent Document 1: P. Bergveld, “Thirty years of ISFETOLOGY What happened in the past 30 years and what may happen in the next 30 years,” Sensors and Actuators B 88 (2003) pp. 1-20    Patent Document 1: Japanese Examined Patent Application Publication No. 7-74793    Patent Document 2: Japanese Unexamined Patent Application Publication No. 2005-207797    Patent Document 3: Japanese Unexamined Patent Application Publication No. 2003-4697    Patent Document 4: PCT Japanese Translation Patent Application Publication No. 2006-503279    Patent Document 5: Japanese Unexamined Patent Application Publication No. 2-184728    Patent Document 6: Japanese Unexamined Patent Application Publication No. 61-118652    Patent Document 7: Japanese Unexamined Patent Application Publication No. 2004-309462